{"id":60913,"date":"2019-12-12T17:47:00","date_gmt":"2019-12-12T09:47:00","guid":{"rendered":"https:\/\/wp-productionenv-bjg9h2g2bgg5b8aa.southeastasia-01.azurewebsites.net\/news\/cobham-introduces-two-new-open-source-processor-ip-cores\/"},"modified":"2019-12-12T17:47:00","modified_gmt":"2019-12-12T09:47:00","slug":"cobham-introduces-two-new-open-source-processor-ip-cores","status":"publish","type":"post","link":"https:\/\/starpath.global\/news\/cobham-introduces-two-new-open-source-processor-ip-cores\/","title":{"rendered":"Cobham Introduces Two New Open Source Processor IP Cores"},"content":{"rendered":"<\/p>\n<p><b><br \/>\nCobham Advanced Electronic Solutions<\/b> revealed Thursday that it has introduced two new offerings to its Cobham Gaisler family of Open Source IP Cores. The new LEON5 IP core implements the SPARC V8 32-bit Instruction Set Architecture (ISA), a 32-bit architecture. And Cobham\u2019s new NOEL-V supports RISC-V, an open, free ISA that enables processor innovation through open standard collaboration. NOEL-V is Cobham\u2019s initial RISC-V solution and the company plans to introduce a range of RISC-V offerings.&nbsp;<\/p>\n<p>Both of Cobham\u2019s new Processor IP Cores will be available for initial download into <strong>Xilinx<\/strong> UltraSCALE FPGAs, and both processors will be fully integrated with Cobham\u2019s GRLIB VHDL IP core library.&nbsp;<\/p>\n<p>\u201cCobham has a longstanding tradition of delivering open source solutions in order to expedite the development of next-generation computing devices for the space industry,\u201d said Kevin Jackson, Cobham\u2019s vice president and general manager, space and semiconductor solutions. \u201cOur new LEON5 achieves a major improvement in terms of compute performance, while simultaneously allowing a smooth upgrade path and software re-use for our existing LEON user base.\u201d<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Cobham Advanced Electronic Solutions revealed Thursday that it has introduced two new offerings to its Cobham Gaisler family of Open Source IP Cores. The new LEON5 IP core implements the SPARC V8 32-bit Instruction Set Architecture (ISA), a 32-bit architecture. And Cobham\u2019s new NOEL-V supports RISC-V, an open, free ISA that enables processor innovation through [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":60914,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"inline_featured_image":false,"footnotes":"","_links_to":"","_links_to_target":""},"categories":[2],"tags":[],"class_list":["post-60913","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"acf":[],"_links":{"self":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/posts\/60913"}],"collection":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/comments?post=60913"}],"version-history":[{"count":0,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/posts\/60913\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/media\/60914"}],"wp:attachment":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/media?parent=60913"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/categories?post=60913"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/tags?post=60913"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}