{"id":61305,"date":"2019-10-19T00:22:28","date_gmt":"2019-10-18T16:22:28","guid":{"rendered":"https:\/\/wp-productionenv-bjg9h2g2bgg5b8aa.southeastasia-01.azurewebsites.net\/news\/seakr-selects-rambus-serdes-and-security-ip-solutions\/"},"modified":"2019-10-19T00:22:28","modified_gmt":"2019-10-18T16:22:28","slug":"seakr-selects-rambus-serdes-and-security-ip-solutions","status":"publish","type":"post","link":"https:\/\/starpath.global\/news\/seakr-selects-rambus-serdes-and-security-ip-solutions\/","title":{"rendered":"Seakr Selects Rambus SerDes and Security IP Solutions"},"content":{"rendered":"<\/p>\n<p><strong>Seakr Engineering<\/strong> selected <strong>Rambus<\/strong>\u2018 28G Multi-protocol LR SerDes PHY and the CryptoManager Root of Trust for its next-generation Application-Specific Integrated Circuit (ASIC) and Field Programmable Gate Arrays (FPGA) designs.<\/p>\n<p>The 28G Multi-protocol LR SerDes PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account to help optimize performance and flexibility. The CryptoManager Root of Trust is a family of co-processors that provides a foundation for system security anchored in hardware and protects against a wide range of attacks with anti-tamper and security techniques.<\/p>\n<p>\u201cWe\u2019re delighted that Seakr has chosen Rambus high-speed interface and defense-grade security cores to provide their customers innovative and silicon-proven technologies,\u201d said Sean Fan, chief operating officer at Rambus. \u201cLeading-edge IP solutions are mission critical to addressing the system design challenges for aerospace and satellite communications. Rambus best-in-class power, performance and area (PPA), including versatile and multi-protocol SerDes solutions and silicon-proven architecture were key differentiators in Seakr\u2019s decision.\u201d<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Seakr Engineering selected Rambus\u2018 28G Multi-protocol LR SerDes PHY and the CryptoManager Root of Trust for its next-generation Application-Specific Integrated Circuit (ASIC) and Field Programmable Gate Arrays (FPGA) designs. The 28G Multi-protocol LR SerDes PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account to help optimize performance and flexibility. [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":61306,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"inline_featured_image":false,"footnotes":"","_links_to":"","_links_to_target":""},"categories":[2],"tags":[],"class_list":["post-61305","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"acf":[],"_links":{"self":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/posts\/61305"}],"collection":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/comments?post=61305"}],"version-history":[{"count":0,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/posts\/61305\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/media\/61306"}],"wp:attachment":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/media?parent=61305"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/categories?post=61305"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/tags?post=61305"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}