{"id":6918,"date":"2024-05-15T00:19:40","date_gmt":"2024-05-14T16:19:40","guid":{"rendered":"https:\/\/wp-productionenv-bjg9h2g2bgg5b8aa.southeastasia-01.azurewebsites.net\/news\/frontgrade-gaisler-to-design-risc-v-processor-for-space-applications-under-esa-contract\/"},"modified":"2024-05-15T00:19:40","modified_gmt":"2024-05-14T16:19:40","slug":"frontgrade-gaisler-to-design-risc-v-processor-for-space-applications-under-esa-contract","status":"publish","type":"post","link":"https:\/\/starpath.global\/news\/frontgrade-gaisler-to-design-risc-v-processor-for-space-applications-under-esa-contract\/","title":{"rendered":"Frontgrade Gaisler to Design RISC-V Processor for Space Applications Under ESA Contract"},"content":{"rendered":"<p style=\"text-align: center;\" itemprop=\"image\" itemscope=\"\" itemtype=\"https:\/\/schema.org\/ImageObject\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/cdn.satnow.com\/news\/front_C_638512694704859628.jpg\" width=\"712\" height=\"377\" alt=\"Frontgrade Gaisler to Design RISC-V Processor for Space Applications Under ESA Contract\" class=\"imageload removeImageattr\" data-original=\"https:\/\/cdn.satnow.com\/news\/front_C_638512694704859628.jpg\" style=\"opacity: 1.54212e-05;\"><meta itemprop=\"url\" content=\"https:\/\/cdn.satnow.com\/news\/front_C_638512694704859628.jpg\"><meta itemprop=\"width\" content=\"712\"><meta itemprop=\"height\" content=\"377\"><\/p>\n<p>Under a contract with the European Space Agency (ESA), <strong><\/strong>Frontgrade Gaisler<strong><\/strong> is designing a new RISC-V processor tailored to meet the requirements of microcontrollers for the space industry. As an open instruction set architecture (ISA), RISC-V\u2019s inherent configurability and efficiency provide the ideal foundation to drive innovation forward in critical sectors of the space computing landscape.<\/p>\n<p>\u201cBuilding on over 25 years of successfully using the SPARC open ISA in space, this effort is an important step forward in the transition to the emerging and equally open RISC-V architecture,\u201d said <strong>Roland Weigand, Technical Officer at ESA<\/strong>. \u201cRISC-V is the preferred architecture across a wide range of space products, from microcontrollers to advanced SoC-FPGAs and high-performance microprocessors for on-board data processing.\u201d<\/p>\n<p>For this project, Frontgrade Gaisler is concentrating on deterministic operation and minimal latency so that the new RISC-V processor IP will execute tasks predictably, reliably, and quickly respond to input stimuli. With these additional benefits, the processor can be integrated into radiation-hardened microcontrollers and field-programmable gate arrays (FPGAs) that support space missions. This model will extend the RISC-V ecosystem and complement the <strong>NOEL-V RISC-V processor<\/strong>, which shares the focus on space applications with an emphasis on high-performance capabilities.<\/p>\n<p>&#8220;Frontgrade Gaisler has decades of experience supplying the space industry with products that implement open standards, and now we\u2019re applying our proven know-how to bring RISC-V advancements to the space industry,&#8221; said <strong>Sandi Habinc, General Manager at Frontgrade Gaisler.<\/strong> \u201cOur team is committed to providing tangible benefits that help progress and grow the entire space community and enable new types of space missions.\u201d<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Under a contract with the European Space Agency (ESA), Frontgrade Gaisler is designing a new RISC-V processor tailored to meet the requirements of microcontrollers for the space industry. As an open instruction set architecture (ISA), RISC-V\u2019s inherent configurability and efficiency provide the ideal foundation to drive innovation forward in critical sectors of the space computing [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"inline_featured_image":false,"footnotes":"","_links_to":"","_links_to_target":""},"categories":[2],"tags":[85,111],"class_list":["post-6918","post","type-post","status-publish","format-standard","hentry","category-news","tag-fpgas","tag-microcontrollers"],"acf":[],"_links":{"self":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/posts\/6918"}],"collection":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/comments?post=6918"}],"version-history":[{"count":0,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/posts\/6918\/revisions"}],"wp:attachment":[{"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/media?parent=6918"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/categories?post=6918"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/starpath.global\/blog\/wp-json\/wp\/v2\/tags?post=6918"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}